Linking frame data by inserting qualifiers in control blocks

ABSTRACT

A method and system for reducing memory accesses by inserting qualifiers in control blocks. In one embodiment, a system comprises a processor configured to process frames of data. The processor may comprise a plurality of buffers configured to store frames of data where each frame of data may be associated with a frame control block. Each frame control block associated with a frame of data may be associated with one or more buffer control blocks. Each control block, e.g., frame control block, buffer control block, may comprise one or more qualifier fields that comprise information unrelated to the current control block. Instead, qualifiers may comprise information related to an another control block. The last frame control block in a queue as well as the last buffer control block associated with a frame control block may comprise fields with no information thereby reducing memory accesses to access information in those fields.

CROSS REFERENCE TO RELATED APPLICATIONS

The present invention is related to the following U.S. patentapplications which are incorporated herein by reference:

Ser. No. ______ (Attorney Docket No. RAL920000091US1) entitled“Assignment of Packet Descriptor Field Positions in a Network Processor”filed ______.

Ser. No. ______ (Attorney Docket No. RAL920000092US1) entitled “StoringFrame Modification Information in a Bank in Memory” filed ______.

Ser. No. ______ (Attorney Docket No. RAL920000096US1) entitled“Efficient Implementation of Error Correction Code Scheme” filed ______.

TECHNICAL FIELD

The present invention relates to the field of a networking communicationsystem, and more particularly to inserting qualifiers in control blocksto reduce memory accesses and thereby improve the efficiency of thebandwidth of the memory.

BACKGROUND INFORMATION

A packet switching network has switching points or nodes fortransmission of data among senders and receivers connected to thenetwork. The switching performed by these switching points is in factthe action of passing on packets or “frames” of data received by aswitching point or node to a further node in the network. Such switchingactions are the means by which communication data is moved through thepacket switching network.

Each node may comprise a packet processor configured to process packetsor frames of data. The packet processor may comprise a data storageunit, e.g., Double Data Rate Static Random Access Memory (DDR SRAM),configured with a plurality of buffers to store frame data. Each frameof data may be associated with a Frame Control Block (FCB) configured todescribe the corresponding frame of data. Each FCB may be associatedwith one or more Buffer Control Blocks (BCBs) where each BCB associatedwith an FCB may be associated with a buffer in the data storage unit. ABCB may be configured to describe the associated buffer. Typically, FCBsand BCBs comprise various fields of information where the fields ofinformation in FCBs and BCBs are each supplied by a separate memory,e.g., Quadruple Data Rate Static Random Access Memory (QDR SRAM), in thepacket processor. That is, the fields of information in FCBs and BCBsmaybe obtained by accessing a separate memory, e.g., QDR SRAM, in thepacket processor.

It would therefore be desirable to reduce the number of accesses to aparticular memory, e.g., QDR SRAM, that supplies information to thefields of FCBs or BCBs thereby improving the efficiency of the bandwidthof the memory, e.g., QDR SRAM.

SUMMARY

The problems outlined above may at least in part be solved in someembodiments by inserting qualifiers in control blocks, e.g., framecontrol blocks, buffer control blocks, that comprise informationunrelated to the current control block. Instead, qualifiers in controlblocks, e.g., frame control blocks, buffer control blocks, may compriseinformation related to another control block or to a buffer associatedwith a next control block. The last frame control block in a queue inthe packet processor as well as the last buffer control block associatedwith a frame control block may comprise fields with no informationthereby reducing memory accesses to a memory, e.g., QDR SRAM, to accessinformation to be inserted in those fields. Subsequently, the bandwidthof the memory, e.g., QDR SRAM supplying information to those fields isimproved.

In one embodiment, a system comprises a packet processor configured toprocess packets, i.e., frames, of data. The processor may comprise aplurality of buffers configured to store frames of data where each frameof data may be associated with a frame control block. Each frame controlblock associated with a frame of data may be associated with one or morebuffer control blocks. Each buffer control block associated with a framecontrol block may be associated with a particular buffer of theplurality of buffers. The processor may further comprise a plurality ofqueues configured to temporarily store one or more frame control blocks.Each control block, e.g., frame control block, buffer control block, maycomprise one or more qualifier fields that comprise information relatedto a particular buffer in the plurality of buffers.

Each frame control block may comprise one or more qualifier fields wherethe one or more qualifier fields comprise information unrelated to acurrent frame control block. In all but the last frame control block ina particular queue, the one or more qualifier fields may compriseinformation as to the byte count length of the one or more buffercontrol blocks associated with a next frame control block. In the one ormore frame control blocks in a particular queue, the one or morequalifier fields may comprise information as to a starting byte positionand to an ending byte position of framed data stored in a particularbuffer associated with the first buffer control block which isassociated with the frame control block.

In another embodiment of the present invention, each buffer controlblock may comprise one or more qualifier fields. In all but the lastbuffer control block associated with a frame control block, the one ormore qualifier fields may comprise information as to a starting byteposition and to an ending byte position of frame data stored in aparticular buffer associated with a next buffer control block.

The foregoing has outlined rather broadly the features and technicaladvantages of the present invention in order that the detaileddescription of the invention that follows may be better understood.Additional features and advantages of the invention will be describedhereinafter which form the subject of the claims of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

A better understanding of the present invention can be obtained when thefollowing detailed description is considered in conjunction with thefollowing drawings, in which:

FIG. 1 illustrates a packet processor configured in accordance with thepresent invention;

FIG. 2 illustrates a data flow unit configured in accordance with thepresent invention;

FIG. 3 is a diagram illustrating the reduction of memory accesses bylinking frame data with qualifiers in control blocks; and

FIG. 4 is a flowchart of a method for reducing memory accesses bylinking frame data with qualifiers in control blocks.

DETAILED DESCRIPTION

The present invention comprises a method and system for reducing memoryaccesses by inserting qualifiers in control blocks. In one embodiment, asystem comprises a packet processor configured to process packets, i.e.,frames, of data. The processor may comprise a plurality of buffersconfigured to store frames of data where each frame of data may beassociated with a frame control block. Each frame control blockassociated with a frame of data may be associated with one or morebuffer control blocks. Each buffer control block associated with a framecontrol block may be associated with a particular buffer of theplurality of buffers. Each control block, e.g., frame control blocks,buffer control blocks, may comprise one or more qualifier fields. Theone or more qualifier fields may comprise information unrelated to thecurrent control block. Instead, qualifiers in control blocks, e.g.,frame control blocks, buffer control blocks, may comprise informationrelated to another control block. By inserting qualifiers storinginformation related to another control block, the last frame controlblock in a queue in the packet processor as well as the last buffercontrol block associated with a frame control block may comprise fieldswith no information thereby reducing memory accesses to a memory, e.g.,QDR SRAM, to access information to be inserted in those fields.Subsequently, the bandwidth of the memory, e.g., QDR SRAM, supplyinginformation to those fields is improved.

FIG. 1—Packet Processor

FIG. 1 illustrates an embodiment of the present invention of a packetprocessor 100. Packet processor 100 may comprise a data flow unit 110configured to receive digital packets, i.e., frames, of data, from aparticular switch (not shown) or port (not shown) of a packet switchingnetwork and transmit the digital packets, i.e., frames, of data toanother switch or port, e.g., switch/port 120, in the packet switchingnetwork. Each frame of data may be associated with a Frame Control Block(FCB) where the FCB describes the associated frame of data. Each FCBassociated with a frame of data may be associated with one or moreBuffer Control Blocks (BCBs) where each BCB associated with an FCB maybe associated with a buffer in a data storage unit 140. A BCB may beconfigured to describe the buffer associated with the next chained BCBas described in the description of FIGS. 3 and 4. In one embodiment,data flow unit 110 may reside on an integrated circuit, i.e., integratedchip. Data flow unit 110 may be coupled to data storage unit 140configured to temporarily store frames of data received by data flowunit 110 from a switch (not shown) or port (not shown) in the packetswitching network. Data flow unit 110 may further be coupled to ascheduler 130 configured to schedule frames of data to be transmittedfrom data flow unit 110 to switch/port 120. In one embodiment, scheduler130 may reside on an integrated circuit, i.e., integrated chip.Furthermore, data flow unit 110 may further be coupled to an embeddedprocessor 150 configured to process frames of data received by data flowunit 110.

FIG. 2—Data Flow Unit

FIG. 2 illustrates an embodiment of the present invention of data flowunit 110. Data flow unit 110 may comprise a receiver controller 203configured to receive and temporarily store packets, i.e., frames, ofdata received from a switch (not shown) or port (not shown) in a packetswitching network. Data flow unit 110 may further comprise a transmittercontroller 201 configured to modify the frame data as well as transmitthe modified frame data to a switch (not shown) or port (not shown) in apacket switching network. Data flow unit 110 may further comprise anembedded processor interface controller 202 configured to exchangeframes to be processed by embedded processor 150.

Packets, i.e., frames, of data may be received by a port/switchinterface unit 221. Port/switch interface unit 221 may receive data froma switch (not shown) in the packet switching network when data flow unit110 operates in an egress mode. Otherwise, port/switch interface unit221 may receive data from a port (not shown) that operates as aninterface to the packet switching network when data flow unit 110operates in an ingress mode. Data received by data flow unit 110 may betemporarily stored in a receiving preparation area memory 220 prior tobeing stored in data storage unit 140 which may be represented by aplurality of slices 205A-F. Slices 205A-F may collectively orindividually be referred to as slices 205 or slice 205, respectively.The number of slices 205 in FIG. 2 is illustrative, and an embodiment ofdata flow unit 110 in accordance with the principles of the presentinvention may have other predetermined number of slices 205. Each slicemay comprise a plurality of buffers. Each slice may represent a slice ofmemory, e.g., Dynamic Random Access Memory (DRAM), so that frame datamay be written into different buffers in different slices in order tomaximize memory bandwidth. A memory arbiter 204 may be configured tocollect requests, e.g., read, write, from receiver controller 203,transmitter controller 201 and embedded processor interface controller202 and subsequently schedule access to particular data store memoryslices, i.e., particular buffers in particular slices 205. For example,receiver controller 203 may be configured to issue write requests tomemory arbiter 204 in order to write received data into individualbuffers in a particular slice 205.

As stated above, frame data may be stored in data storage unit 140,i.e., a plurality of slices 205. In one embodiment, frame data may bestored in one or more buffers in one or more slices 205 in a manner suchthat the data in each particular frame may be recomposed by having thebuffers chained together. That is, data in a particular frame may bestored in one or more buffers that are chained together in the orderthat data is written into the one or more buffers. The chaining of theone or more buffers may be controlled by a Buffer Control Block Unit(BCBU) 208 in a memory 229, e.g., Quadruple Data Rate Static RandomAccess Memory (QDR SRAM), coupled to data flow unit 110. BCBU 208 may beconfigured to comprise the addresses of each of the one or more bufferschained together in the order data was written into buffers. Thedifferent buffers comprising data of the same frames may be linkedtogether by means of pointers stored in BCBU 208.

As stated above, each frame of data may be associated with a FrameControl Block (FCB) where the FCB describes the associated frame ofdata. Frame Control Block Unit 1 (FCBU1) 209 in a memory 210, e.g., QDRSRAM, maybe configured to store the information, e.g., frame controlinformation, to be filled in the fields of the FCBs. That is, the fieldsof information in FCBs may be obtained by accessing memory 210, i.e.,FCBU1) 209 of memory 210. Additional details regarding FCBU1 209 ofmemory 210 storing fields of information are disclosed in U.S. patentapplication Ser. No. ______ filed on ______, entitled “Assignment ofPacket Descriptor Field Positions in a Network Processor,” AttorneyDocket No. RAL920000091US1, which is hereby incorporated herein byreference in its entirety.

Frame data stored in buffers may be processed by embedded processor 150by transmitting the header of each frame to be processed to embeddedprocessor 150. As stated above, each frame of data may be represented byan FCB. These FCBs may be temporarily stored in G Queues (GQs) 218.Dispatcher logic 217 maybe configured to dequeue the next FCB from GQs218. Once dispatcher logic 217 dequeues the next FCB, dispatcher logic217 issues a read request to memory arbiter 204 to read the data at thebeginning of the frame, i.e., header of the frame, stored in datastorage unit 140 associated with the dequeued FCB. The data read bydispatcher logic 217 is then processed by embedded processor 150.

Once frame data has been processed by embedded processor 150, theprocessed frame data may be temporarily stored in data storage unit 140,i.e., slices 205, by embedded processor logic 216 issuing a writerequest to memory arbiter 204 to write the processed frame data intoindividual buffers in one or more slices 205.

Once frame data has been processed by embedded processor 150, embeddedprocessor logic 216 further issues the FCB associated with the processedframe to scheduler 130. Scheduler 130 may be configured to comprise flowqueues 223 configured to store FCBs. Scheduler 130 may further comprisea Frame Control Block Unit 2 (FCBU2) 225 within a memory 224, e.g., QDRSRAM, configured to operate similarly as FCBU1 209. FCBU2 225 maybeconfigured to store the information to be filled in the fields of theFCBs when the FCBs are temporarily residing in flow queues 223.Additional details regarding FCBU2 225 within memory 224 of scheduler130 storing fields of information are disclosed in U.S. patentapplication Ser. No. ______, filed on ______, entitled “Assignment ofPacket Descriptor Field Positions in a Network Processor,” AttorneyDocket No. RAL920000091US1. Scheduler 130 may be configured to transmitthe FCBs stored in flow queues 223 to Target Blade Queues (TBQs) 215enqueue logic 227 configured to enqueue the received FCBs in TBQs 215.

FCBs queued in TBQs 215 may be scheduled to be dequeued from TBQs 215 byTBQ scheduler 228 and loaded into Port Control Block (PCB) 224. TBQscheduler 228 may be configured to dequeue the next FCB from TBQs 215and enqueue that FCB into PCB 224. Once the next FCB is enqueued intoPCB 224, PCB 224 may issue a read request to memory arbiter 204 to readthe data at the beginning of the frame, i.e., header of the frame,stored in data storage unit 140 associated with the dequeued FCB. Thedata read by PCB 224 may be temporarily stored in data preparation areamemory 214 prior to transmitting the processed frame data to a switch(not shown) or port (not shown) in a packet switching network. It isnoted for clarity that PCB 224 may be configured to read a portion ofthe data stored in the processed frame in each particular read request.That is, the entire data stored in the processed frame may be read inmultiple read requests provided by PCB 224. Once the entire data storedin the processed frame is read, the data storage unit 140 may storeadditional frame data.

Transmitter controller 201 may further comprise a frame alterationpreparation area memory 213 configured to receive commands to modify theprocessed frames temporarily stored in data preparation area memory 214.These commands are commonly referred to as frame modification commandswhich are issued by embedded processor 150 and stored in a particularbank in a particular buffer by embedded processor logic 216. Additionaldetails regarding the storing of frame modification commands in aparticular bank in a particular buffer are disclosed in U.S. patentapplication Ser. No. ______, filed on ______, entitled “Storing FrameModification Information in a Bank in Memory,” Attorney Docket No.RAL920000092US1, which is hereby incorporated herein by reference in itsentirety. In one embodiment, PCB 224 may be configured to retrieve theframe modification commands stored in a particular bank in a particularbuffer and store them in frame alteration preparation area memory 213. AFrame Alteration (FA) logic unit 212 may be configured to execute thecommands stored in frame alteration preparation area memory 213 tomodify the contents of the processed frames temporarily stored in datapreparation area memory 214. Once FA logic 212 has modified the contentsof the processed frames, then modified processed frames may betransmitted through a switch/port interface unit 211. Switch/portinterface unit 211 may transmit data to a port (not shown) that operatesas an interface to the packet switching network when data flow unit 110operates in an egress mode. Otherwise, switch/port interface unit 211may transmit data to a switch (not shown) in the packet switchingnetwork when data flow unit 110 operates in an ingress mode.

Data flow unit 110 may further comprise a Buffer Control Block (BCB)Arbiter 207 configured to arbitrate among different BCB requests fromtransmitter controller 201, embedded processor interface controller 202and receiver controller 203 to read from or write to BCBU 208. BCBArbiter 207 may be configured to schedule different accesses in order toutilize memory bandwidth as efficiently as possible. Data flow unit 110may further comprise a Frame Control Block (FCB) Arbiter 206 configuredto arbitrate among different FCB requests from embedded processorinterface controller 202, receiver controller 203 and transmittercontroller 201 to read from or write to FCBU1 209.

As stated above, each frame of data may be associated with an FCB. Asthe processed frames are read from data storage unit 140, e.g., DDRDRAM, and the processed frames are modified and transmitted to a switch(not shown) or a port (not shown) in the packet switching network, theFCB associated with such processed frame ceases to represent thatparticular frame of data. Once the FCB is no longer associated withframe data, the FCB may be stored in a FCB free queue 222 within FCBArbiter 206. FCB free queue 222 may be configured to comprise aplurality of FCBs that are no longer associated with particular framedata. It is noted that FCB free queue 222 may comprise any number ofFCBs that are no longer associated with particular frame data. Once dataflow unit 110 receives a packet, i.e., frame, of data, a ReassemblyControl Block (RCB) 219 of receiver controller 203 may associate aparticular FCB from FCB free queue 222 with the received frame of datawhere the newly associated FCB may then be queued in GQs 218 by RCB 219.

As stated above, each frame of data may be associated with an FCB. EachFCB associated with a frame of data may be associated with one or moreBCBs where each BCB associated with an FCB may be associated with aparticular buffer of data storage unit 140. A BCB may be configured todescribe the buffer associated with the next chained BCB as described inthe discussion of FIGS. 3 and 4. Once the processed frame data stored ina buffer of data storage unit 140 has been retrieved by transmittercontroller 201 and subsequently modified and transmitted to a switch(not shown) or port (not shown) in the packet switching network, the BCBassociated with that particular buffer that no longer includes any framedata ceases to comprise any valid information. That is, the BCBassociated with the particular buffer that no longer includes any framedata includes data that is no useful since the particular bufferassociated with the BCB no longer includes any frame data. Once the BCBceases to comprise any valid information, i.e., once the frame data in aparticular buffer has been transmitted, the BCB may be stored in a BCBfree queue 226 within BCB Arbiter 206. BCB free queue 226 may beconfigured to comprise a plurality of BCBs that do not comprise anyvalid information. It is noted that BCB free queue 226 may comprise anynumber of BCBs that do not comprise any valid information. Once receivercontroller 203 receives frame data, RCB 219 of receiver controller 203may retrieve a BCB in BCB free queue 226 so that RCB 219 may write thereceived frame data in the particular buffer associated with the BCBretrieved from BCB free queue 226.

As stated in the Background Information section, FCBs and BCBs maycomprise various fields of information where the fields of informationare supplied by a separate memory 210, i.e., FCBU1 209 of memory 210,and memory 229, i.e., BCBU 208 of memory 229, respectively. That is, thefields of information in FCBs may be obtained by accessing memory 210,i.e., FCBU1 209 of memory 210. The fields of information in BCBs may beobtained by accessing memory 229, i.e., BCBU 208 of memory 229. It wouldtherefore be desirable to reduce the number of accesses to memories 210and 229, e.g., QDR SRAM, that supplies information to the fields of FCBsand BCBs, respectively, thereby improving the efficiency of thebandwidth of memories 210 and 229. A diagram illustrating the reductionof memory accesses to memories 210 and 229 by inserting qualifiers inthe fields of control blocks is described below.

FIG. 3—Diagram Illustrating the Reduction of Memory Accesses by LinkingFrame Data with Qualifiers in Control Blocks

FIG. 3 schematically illustrates an exemplary set 300 of control blocksdepicting the inclusion of qualifiers in control blocks, e.g., FCB, BCB,in order to reduce accesses to memories 210 and 229 in accordance withthe principles of the present invention. As stated above, FCBs maytemporarily reside in a queue 305 which may be one of the followingqueues: FCB free queue 222, GQs 218, flow queues 223, and TBQs 215. Ineach of the above stated queues, i.e., FCB free queue 222, GQs 218, flowqueues 223, TBQs 215, the queue has a control block commonly referred toas a Queue Control Block (QCB) 301 comprising information as to thenumber of FCBs that currently reside in that particular queue. It isnoted that BCB free queue 226 may also comprise QCB 301. It is furthernoted that QCB 301 may comprise other information than the number ofFCBs that currently reside that particular queue.

Referring to FIG. 3, QCB 301 may comprise a head field 302, a tail field303 and a count field 304. Head field 302 may comprise an FCB Address(FCBA) of a first FCB, e.g., FCB 310A, located in the queue, e.g., FCBfree queue 222, GQs 218, flow queues 223, TBQs 215, comprising QCB 301.(In the exemplary set 300 of FIG. 3, the notation (X) connected tocertain fields of QCB 301, FCB 310A and FCB 310B, is used to denote thatthe particular field points to FCBX or comprises the byte count lengthof BCBsX.). Head field 302 may further comprise the Byte Count (BCNT) ofthe one or more BCBs, e.g., BCBs 320A-C, associated with the first FCB,e.g., FCB 310A, located in the queue, e.g., FCB free queue 222, GQs 218,flow queues 223, TBQs 215. The BCNT in head field 302 may be referred toas an qualifier as it identifies the byte count length of the one ormore BCBs, e.g., BCBs 320A-C, associated with the first FCB, e.g., FCB310A, in the queue 305 comprising QCB 301. Tail field 303 may comprisethe FCB Address (FCBA) of last FCB, e.g., FCB 310B, in queue 305, e.g.,FCB free queue 222, GQs 218, flow queues 223, TBQs 215, comprising QCB301. Count field 304 may comprise the number of FCBs in queue 305comprising QCB 301. Because in the exemplary set 300 of Figure there aretwo FCBs, e.g., FCB 310A-B, in queue 305 comprising QCB 301, count field304 comprises the number two. As an ordinary skilled artisan wouldrecognize, it is noted that the queues, e.g., FCB free queue 222, GQs218, flow queues 223, TBQs 215, may comprise any number of FCBs and thatFIG. 3 is illustrative. It is further noted that FCBs 310A-B maycollectively or individually be referred to as FCBs 310 or FCB 310,respectively.

Each FCB 310 may comprise two entries or rows of fields. In each FCB310, the first entry may comprise a field comprising a pointer to theNext FCB Address (NFA). The first entry may further comprise a fieldcomprising the Byte Count (BCNT) length of the one or more BCBsassociated with the next FCB 310. That is, instead of FCBs 310 storingthe Byte Count length (BCNT) of the one or more BCBs associated with thecurrent FCB 310, the BCNT field stores the byte count length of the oneor more BCBs associated with the next FCB 310. For example, FCB 310Acomprises the FCB address of the following FCB 310, e.g., FCB 310B, inthe NFA field as well as the byte count length of the one or more BCBs,e.g., BCBs 320 D-F, associated with the following FCB 310, e.g., FCB310B, in the BCNT field. The BCNT field may be referred to as anqualifier as it identifies the byte count length of the one or moreBCBs, e.g., BCBs 320D-F, associated with FCB 310B identified in the NFAfield, i.e., the next FCB 310 in the chain of FCBs 310. FCB 310B doesnot comprise any information in the NFA field or in the BCNT field asthere are no more FCBs 310 following FCB 310B. (This is denoted in theexemplary set 300 of FIG. 3 by “empty” parentheses “( )”). By notstoring information in the NFA field and in the BCNT field of FCB 310B,memory accesses to memory 210 are reduced thereby improving theefficiency of the bandwidth of memory 210.

In each FCB 310, the second entry may comprise the fields of the FirstBCB Address (FBA) of the first BCB associated with that particular FCB,the Starting Byte Position (SBP) of the frame data stored in a bufferassociated with the first BCB, and the Ending Byte Position (EBP) of theframe data stored in the buffer associated with the first BCB. Each FCBmaybe associated with one or more BCBs. Referring to FIG. 3, FCB 310A isassociated with BCBs 320A-C. FCB 310B is associated with BCBs 320D-F. Itis noted that FCBs may be associated with any number of BCBs and thatFIG. 3 is illustrative, as would be recognized by an artisan of ordinaryskill. It is further noted that BCBs 320A-F may collectively orindividually be referred to as BCBs 320 or BCB 320, respectively. EachBCB 320 maybe associated with a particular buffer in data storage unit140. For example, BCB 320A is associated with buffer 330A. BCB 320B isassociated with buffer 330B. BCB 320C is associated with buffer 330C.BCB 320D is associated with buffer 330D. BCB 320E is associated withbuffer 330E. BCB 320F is associated with buffer 330F. Buffers 330A-F maycollectively or individually be referred to as buffers 330 or buffer330, respectively. It is noted that data storage unit 140 of packetprocessor 100 may comprise any number of slices 205 comprising anynumber of buffers 330. It is further noted that since there may be anynumber of buffers 330 there may be any number of BCBs 320 associatedwith those buffers 330. It is further noted that in one embodiment, eachBCB 320 maybe associated with a particular buffer 330 in data storageunit 140.

Referring to FCB 310A, the FBA field in the second entry may comprisethe address of the first BCB 320, e.g., BCB 320A, associated with FCB310A. FCB 310A may further comprise an SBP field storing the startingaddress of the frame data stored in the buffer 330, e.g., buffer 330A,associated with the first BCB 320, e.g., BCB 320A. FCB 310A may furthercomprise an EBP field storing the ending address of the frame datastored in the buffer 330, e.g., buffer 330A, associated with the firstBCB 320, e.g., BCB 320A. The SBP and EBP fields may be referred to asqualifiers as they comprise information about the starting byte positionand ending byte position of the frame data associated with the first BCB320, e.g., BCB 320A, and not information about the current FCB 310,e.g., FCB 310A. Similarly, FCB 310B may comprise an FBA field in thesecond entry which comprises the address of the first BCB 320, e.g., BCB320D, associated with FCB 310B. FCB 310B may further comprise an SBPfield storing the starting address of the frame data stored in thebuffer 330, e.g., buffer 330D, associated with the first BCB 320, e.g.,BCB 320D. FCB 310B may further comprise an EBP field storing the endingaddress of the frame data stored in the buffer 330, e.g., buffer 330D,associated with the first BCB 320, e.g., BCB 320D. The SBP and EBPfields may be referred to as qualifiers as they comprise informationabout the starting byte position and ending byte position of the framedata associated with the first BCB 320, e.g., BCB 320D, and notinformation about the current FCB 310, e.g., FCB 310B.

As stated above, each FCB 310 may be associated with one or more BCBs320. Referring to FIG. 3, FCB 310A is associated with BCBs 320A-C andFCB 310B is associated with BCBs 320D-F. Each BCB 320 may comprise threefields that are similar to the three fields in the second entry of FCBs310. Each BCB 320 may comprise a pointer to the Next BCB Address (NBA)as well as the fields of SBP and EBP which are the starting and endingbyte positions of the buffer 330 associated with the next BCB. The SBPand EBP fields may be referred to as qualifiers as they store thestarting byte position and ending byte position of the buffer 330, e.g.,buffer 330B, associated with the next BCB 320, e.g., BCB 320C. That is,instead of storing the starting and ending byte positions of the buffer330, e.g., buffer 330B, associated with the current BCB 320, e.g., BCB320B, thereby resulting an extra write access to memory 229, thestarting and ending byte positions of the buffer 330, e.g., buffer 330B,associated with the next BCB 320, e.g., BCB 320B, is stored in the SBPand EBP fields, respectively, in the previous BCB 320, e.g., BCB 320A.

For example, BCB 320A comprises the BCB address of the next BCB 320,e.g., BCB 320B, in the NBA field as well as the starting byte positionof the frame data stored in the buffer 330, e.g., buffer 330B,associated with the next BCB 320, e.g., BCB 320B, in the SBP field andthe ending byte position of the frame data stored in the buffer 330,e.g., buffer 330B, associated with the next BCB, 320, e.g., BCB 320B, inthe EBP field. BCB 320B comprises the BCB address of the next BCB 320,e.g., BCB 320C, in the NBA field as well as the starting byte positionof the frame data stored in the buffer 330, e.g., buffer 330C,associated with the next BCB, e.g., BCB 320C, in the SBP field and theending byte position of the frame data stored in the buffer 330, e.g.,buffer 330C, associated with the next BCB 320, e.g., BCB 320C, in theEBP field. In the last BCB 320, e.g., BCB 320C, associated with an FCB,310, e.g., FCB 310A, there is no information in the fields of NBA, SBPand EBP since there are no more BCBs 320 following the last BCB 320,e.g., BCB 320C. By not storing information in the NBA, SBP and EBPfields of the last BCB 320, e.g., BCB 320C, there is no information tobe written into the fields of the last BCB 320, e.g., BCB 320C,associated with an FCB 310, e.g., FCB 310A, thereby reducing memoryaccesses to memory 229 and improving the efficiency of the bandwidth ofmemory 229.

FIG. 4—Method for Reducing Memory Accesses by Linking Frame Data withQualifiers in Control Blocks

FIG. 4 illustrates a flowchart of one embodiment of the presentinvention of a method 400 for reducing memory accesses to memories 210and 229 by linking frame data with qualifiers in control blocks, e.g.,FCBs 310, BCBs 320.

In step 401, a frame of data may be received from a switch (not shown)or a port (not shown) in a packet switching network and temporarilystored in receiving preparation area memory 220 by receiver controller203.

In step 402, RCB 219 of receiver controller 203 may be then beconfigured to lease one or more BCBs 320 from BCB free queue 226 (FIG.2). A BCB may be said to be “leased” from BCB free queue 226 as the BCBmay be temporarily removed from BCB free queue 226 during the “lifecycle” of the FCB. Additional details regarding the “life cycle” of theFCB are disclosed in U.S. patent application Ser. No. ______, filed on______, entitled “Assignment of Packet Descriptor Field Positions in aNetwork Processor,” Attorney Docket No. RAL920000091US1. RCB 219 maythen write the received data in one or more particular buffers 330associated with the one or more BCBs 320 leased from BCB free queue 226.In one embodiment, RCB 219 may issue one or more write requests tomemory arbiter 204 in order to write the received frame data into one ormore buffers 330 associated with the one or more BCBs leased from BCBfree queue 226.

As stated above, each particular buffer 330 may be associated with aparticular BCB 320. BCB 320 may be configured as illustrated in FIG. 3where BCB 320 may comprise the field of a Next BCB Address (NBA) whichcomprises a pointer to the next BCB 320 address as well as the fields ofSBP and EBP which are the starting and ending byte positions of thebuffer 330 associated with the next BCB 320. The SBP and EBP fields maybe referred to as qualifiers as they store the starting byte positionand ending byte position of the buffer 330 associated with the next BCB320. That is, instead of storing the starting and ending byte positionsof the buffer 330, e.g., buffer 330A (FIG. 3), associated with thecurrent BCB 320, e.g., BCB 320A (FIG. 3), thereby resulting an extrawrite access to memory 229, the starting and ending byte positions ofthe buffer 330, e.g., buffer 330B (FIG. 3), associated with the next BCB320, e.g., BCB 320B (FIG. 3), is stored in the SBP and EBP fields,respectively, in the previous BCB 320, e.g., BCB 320A (FIG. 3).

During each lease operation, i.e., each BCB 320 leased from BCB freequeue 226 by RCB 219, RCB 219 may read the head field 302 in QCB 301(FIG. 3) of BCB free queue 226. RCB 219 may then read the NBA field ofthe first BCB 320, e.g., BCB 320A, which may comprise the address of thenext BCB 320 in the BCB free queue 226 to retrieve. Head field 302 ofQCB 301 may subsequently be updated by RCB 219 so that the address inthe head field 302 is the address of the next BCB 320 that may beretrieved during the next lease operation. The count field 304 of QCB301 of BCB free queue 226 may then be decremented to indicate that a BCB320 has been retrieved from BCB free queue 226. Head field 302 of QCB301 may further comprise the Byte Count (BCNT) of the one or more BCBs320, e.g., BCBs 320A-C (FIG. 3), associated with the one or more buffers330, e.g., buffers 330A-C (FIG. 3), storing the frame of data. The BCNTin head field 302 may be referred to as an qualifier as it identifiesthe byte count length of the one or more BCBs 320, e.g., BCBs 320A-C(FIG. 3), associated with the one or more buffers 330, buffers 330A-C(FIG. 3), storing the frame of data and not information about the BCBfree queue 226 comprising QCB 301. QCB 301 may further comprise a tailfield 303 comprising the address of the last FCB, e.g., FCB 310B (FIG.2), located in the queue, e.g., FCB free queue 222.

RCB 219 of receiver controller 203 may associate the one or more BCBs320, e.g. BCBs 320A-C (FIG. 3), with an FCB 310 in step 403. RCB 219 maylease an FCB 310 from FCB free queue 222 (FIG. 2) thereby associatingthe leased FCB 310 with the one or more BCBs 320, e.g., BCBs 320A-C(FIG. 3), that are associated with the one or more buffers 205, e.g.,buffers 205A-C (FIG. 3), storing the frame of data. An FCB may be saidto be “leased” from FCB free queue 222 as the FCB may be temporarilyremoved from FCB free queue 222 during the “life cycle” of the FCB.Additional details regarding the “life cycle” of the FCB are disclosedin U.S. patent application Ser. No. ______, filed on ______, entitled“Assignment of Packet Descriptor Field Positions in a NetworkProcessor,” Attorney Docket No. RAL920000091US1. FCB 310 may beconfigured as illustrated in FIG. 3 with two entries or rows of fields.The first entry may comprise a field comprising a pointer to the NextFCB Address (NFA). The first entry may further comprise a fieldcomprising the Byte Count (BCNT) length of the one or more BCBs 320,e.g., BCBs 320D-F (FIG. 3), associated with the next FCB 310. That is,instead of FCB 310 storing the Byte Count length (BCNT) of the one ormore BCBs 320 associated with the current FCB 310, the BCNT field storesthe byte count length of the one or more BCBs 320 associated with thenext FCB 310. It is noted that the last FCB 310, e.g., FCB 310B (FIG.3), in the queue, e.g., FCB free queue 222 (FIG. 2), does not compriseany information in the NFA field or in the BCNT field as there are nomore FCBs 310 following the last FCB 310, e.g., FCB 310B (FIG. 3), inthe queue, e.g., FCB free queue 222 (FIG. 2). By not storing informationin the NFA field and in the BCNT field of the last FCB 310, e.g., FCB310B (FIG. 3), memory accesses to memory 210 are reduced therebyimproving the bandwidth of memory 210. It is further noted that the lastFCB 310, e.g., FCB 310B (FIG. 3), located in the queue, e.g., FCB freequeue 222 (FIG. 2), may be identified in tail field 303 of QCB 301 (FIG.3) of FCB free queue 222. As stated above, tail field 303 may comprisethe address of the last FCB 310, e.g., FCB 310B (FIG. 2), located in thequeue, e.g., FCB free queue 222.

The second entry of FCB 310 may comprise the fields of the First BCBAddress (FBA) of the first BCB 320, e.g., BCB 320A (FIG. 3), associatedwith that particular FCB 310, the Starting Byte Position (SBP) of theframe data stored in buffer 330, e.g., buffer 330A (FIG. 3), associatedwith the first BCB 320, e.g., BCB 320A (FIG. 3), and the Ending BytePosition (EBP) of the frame data stored in buffer 330, e.g., buffer 330A(FIG. 3), associated with the first BCB 320, e.g., BCB 320A (FIG. 3).The SBP and EBP fields may be referred to as qualifiers as they compriseinformation about the starting byte position and ending byte position ofthe frame data associated with the first BCB 320, e.g., BCB 320A (FIG.3), and not information about the current FCB 310, e.g., FCB 310A (FIG.3).

In the lease operation, RCB 219 may read the head field 302 in QCB 301of FCB free queue 222. Head field 302 may include the address of thefirst FCB 310, e.g., FCB 310A (FIG. 3), to retrieve from FCB free queue222. RCB 219 may then read the NFA field of the first FCB 310, e.g., FCB310A, which may comprise the address of the next FCB 310 in the FCB freequeue 222 to retrieve. Head field 302 of QCB 301 may subsequently beupdated so that the address in head field 302 is the address of the nextFCB 310 that may be retrieved during the next lease operation. The countfield 304 of QCB 301 of FCB free queue 222 may then be decremented toindicate that a FCB 310 has been retrieved from FCB free queue 222 andenqueued in GQs 218.

In step 404, FCB 310 may be enqueued in GQs 218 by RCB 219. Asillustrated in FIG. 3, FCB 310 may comprise the fields of FBA as well asthe qualifiers SBP and EBP in the second entry. Once FCB 310 is enqueuedin GQs 218, the information in these fields are copied from RCB 219. RCB219 may store the starting and ending byte position of the frame data itstored in the first buffer 330, e.g., buffer 330A, associated with thefirst BCB 320, e.g., BCB 320A, associated with the FCB 310, e.g., FCB310A, enqueued in GQs 218 by RCB 219 when RCB 219 writes the receivedframe data into the first buffer 330, e.g., buffer 330A, associated withthe first BCB 320, e.g., BCB 320A, associated with the FCB 310, e.g.,FCB 310A, enqueued in GQs 218 by RCB 219. Furthermore, the BCNT field inthe first entry of FCB 310 maybe copied from RCB 219.

FCB 310 enqueued in GQs 218 may then be chained together with the otherFCBs 310 in GQs 218 in step 405. RCB 219 may read the tail field 303 inQCB 301 of GQs 218 to retrieve the address of the current last FCB 310in GQs 218. The tail field 303 in QCB 301 of GQs 218 may subsequently beupdated by RCB 219 so that the pointer in tail field 303 points to theFCB 310 just enqueued in GQs 218. The count field 304 of QCB 301 of GQs218 may then be incremented by RCB 219 to indicate that an FCB 310 hasbeen retrieved from FCB free queue 222 and enqueued in GQs 218.

In step 406, FCB 310 may be dequeued from GQs 218. Dispatcher logic 217of embedded processor interface controller 202 may read the head field302 of QCB 301 of GQs 218 to retrieve the address of the FCB 310 todequeue. Dispatcher logic 217 may further read the NFA field in the FCB310 to determine the address of the next FCB 310 in GQs 218 to dequeue.Dispatcher logic 217 may be configured to update the head field 302 ofQCB 301 in GQs 218 so that the address in the head field 302 is theaddress of the next FCB 310 that may be dequeued at the next dequeueoperation. The count field 304 of QCB 301 in GQs 218 may be decrementedto indicate that an FCB 301 has been dequeued from GQs 218. The contentsof the dequeued FCB 310 may then be read by dispatcher logic 217 andtransferred to embedded processor 150.

In step 407, the dequeued FCB 310 may be enqueued in TBQs 215. Inanother embodiment, FCB 310 may first be enqueued in flow queues 223 ofscheduler 130 and then dequeued and enqueued in TBQs 215. Additionaldetails regarding enqueing and dequeing the FCB 310 in flow queues 223of scheduler 130 are disclosed in U.S. patent application Ser. No.______, filed on ______, entitled “Assignment of Packet Descriptor FieldPositions in a Network Processor,” Attorney Docket No. RAL920000091US1.

In step 408, the enqueued FCB 310 in TBQs 215 may then be dequeued byTBQ scheduler 228 to be loaded into PCB 224 to be read by PCB 224 asdiscussed in the description of FIG. 2. In particular, the address inthe FBA field of the FCB 310 may be loaded into PCB 224.

In step 409, the frame of data to be transmitted through switch/portinterface unit 211 to a switch (not shown) or a port (not shown) in thepacket switching network may be read from the one or more buffers 330associated with the one or more BCBs 320, e.g., BCBs 320A-C (FIG. 3), byPCB 224. PCB retrieves the address of the first BCB 320, i.e., theaddress included in the FBA field of the FCB 310 dequeued in step 408,that was loaded into PCB 224. The address of the next BCB 320, e.g., BCB320B (FIG. 3), may be located in the NBA field of the first BCB 320,e.g., BCB 320A (FIG. 3).

In step 410, when all the data of a frame is read by PCB from the one ormore buffers 330 of data storage unit 140 that stored the frame of data,the one or more BCBs 320, e.g., BCBs 320A-C (FIG. 3), associated withthe one or more buffers 330, e.g., buffers 330A-C (FIG. 3), are enqueuedin BCB free queue 226. In one embodiment, each BCB 320 may be enqueuedone at a time in BCB free queue 226 as frame data in each associatedbuffer 330 is read by PCB 224.

In step 411, when the one or more BCBs 320, e.g., BCBs 320A-C (FIG. 3),associated with the one or more buffers 330, e.g., buffers 330A-C (FIG.3), have been enqueued in BCB free queue 226, the FCB 310 associatedwith the one or more BCBs 320, e.g., BCBs 320A-C (FIG. 3) is enqueued inFCB free queue 222.

Although the method and system of the present invention are described inconnection with several embodiments, it is not intended to be limited tothe specific forms set forth herein, but on the contrary, it is intendedto cover such alternatives, modifications, and equivalents, as can bereasonably included within the spirit and scope of the invention asdefined by the appended claims. It is noted that the headings are usedonly for organizational purposes and not meant to limit the scope of thedescription or claims.

1-10. (canceled)
 11. A method for reducing memory accesses by insertingqualifiers in control blocks comprising the steps of: receiving a frameof data; leasing one or more buffer control blocks; storing said frameof data in one or more buffers associated with said one or more buffercontrol blocks in a data storage unit; and leasing a frame control blockassociated with said one or more buffer control blocks; wherein saidframe control block comprise one or more qualifier fields, wherein saidone or more qualifier fields in said frame control block compriseinformation related to one of said one or more buffers in said datastorage unit.
 12. The method as recited in claim 11 further comprisingthe step of: enqueing said frame control block in a queue.
 13. Themethod as recited in claim 11, wherein said one or more qualifier fieldsin said frame control block comprise information as to an address of oneof said one or more buffer control blocks associated with current framecontrol block.
 14. The method as recited in claim 11, wherein said oneor more qualifier fields in said frame control block compriseinformation as to a starting byte position and to an ending byteposition of data stored in said one of said one or more buffers storingsaid frame of data.
 15. The method as recited in claim 1 1, wherein eachof said one or more buffer control blocks comprise one or more qualifierfields, wherein said one or more qualifier fields in all but a lastbuffer control block of said one or more buffer control blocksassociated with said frame control block comprise information as to astarting byte position and to an ending byte position of data stored inone of said one or more buffers associated with a next buffer controlblock.
 16. The method as recited in claim 12, wherein said queuecomprises a control block, wherein said control block in said queuecomprises a head field, wherein said head field in said queue comprisesan address of a first frame control block in said queue.
 17. The methodas recited in claim 16, wherein said head field in said queue furthercomprises a qualifier, wherein said qualifier comprises information asto a byte count length of one or more buffer control blocks associatedwith said first frame control block.
 18. The method as recited in claim16, wherein said control block of said queue further comprises a tailfield, wherein said tail field comprises an address of a last framecontrol block in said queue.
 19. The method as recited in claim 16,wherein said control block of said queue further comprises a countfield, wherein said count field comprises a number of frame controlblocks in said queue.